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6500 Data Windowing Examples Hi/fn(R) supplies two of the Internet's most important raw materials: compression and encryption. Hi/fn is also the world's first company to put both on a single chip, creating a processor that performs compression and encryption at a faster speed than a conventional CPU alone could handle, and for much less than the cost of a Pentium or comparable processor. Hi/fn, Inc. 750 University Avenue Los Gatos, CA 95032 info@hifn.com http://www.hifn.com Tel: 408-399-3500 Fax: 408-399-3501 Hi/fn Applications Support Hotline: 408-399-3544
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6500 Data Windowing Examples
Table of Contents
1 2 3 4 5 Overview ......................................................................................................5 Little-endian CPU, little-endian data in memory ..........................................6 Little-endian CPU, big-endian data in memory ............................................7 Big-endian CPU, big-endian data in memory ...............................................8 Big-endian CPU, little-endian data in memory.............................................9
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6500 Data Windowing Examples
1
Overview
The examples in this Application Note explain in detail how the byte ordering and word ordering windows of the 6500 Public Key Processor are used in specific instances. The register windows of the 6500 are actually very simple, requiring a very small amount of gates on the chip, but at first it may be bit difficult to understand intuitively the effect of (and even the need for) these transformations. In general, for any given system, it is likely that only a single register window needs to be used. It is hoped that the detailed real-life examples given here will help make it clear which window(s) should be used for a particular system. Internally to the 6500 engines, no windowing bits are used or needed when accessing the data registers. The two windowing bits only affect transfers between the internal data registers and the outside world (e.g., the host CPU). The windowing bits do not affect CPU transfers to/from 6500 registers other than the data registers. Bit 13 of the register address controls whether bits 2..6 of the register address presented to the chip are logically inverted when presented to the internal 6500 register array. This transformation has the effect of reversing the order of the 32-bit words within a register from the perspective of the outside world. Inside the 6500, this windowing bit 13 merely is used to XOR address bits 2..6 when the address accesses a data register. Bit 14 of the register address controls whether the 32-bit word transferred over the CPU bus has a byte reversal (endian conversion) applied to it. The 6500 uses little-endian byte ordering internally, so this windowing bit allows automatic (and dynamic) endian conversion if necessary. To keep the examples tractable, the integer values used below are smaller (e.g., 256 bits) than public key arithmetic values of practical interest (e.g., 1024 bits), but the same principles illustrated here can be extended to larger values in obvious ways. In all cases, it is assumed in the discussions below that data bus bit 0 of the 6500 is connected to the least significant bit of the CPU data bus, and that data bus bit 31 of the 6500 is connected to the most significant bit of the CPU data bus. Example: Suppose that we wish to transfer a 256-bit integer value
N = 0x8F8E8D8C8B8A89888786858483828180000102030405060708090A0B0C0D0E0F
into or out of the 6500 register space. The syntax used to represent this value is C-like;the most significant 8 bits of N are 0x8F, and the least significant byte of N is 0x0F. Internal to the 6500, left-aligned little-endian ordering is used for modular arithmetic. Thus, if the register r3 (offset 0x180) holds N, the internal registers are: ________________________________________________________________ APPLICATION NOTE AN-0005-02 Page 5
6500 Data Windowing Examples
internal internal internal internal internal internal internal internal
register register register register register register register register
offset offset offset offset offset offset offset offset
0x01E0 0x01E4 0x01E8 0x01EC 0x01F0 0x01F4 0x01F8 0x01FC
= = = = = = = =
0x0C0D0E0F 0x08090A0B 0x04050607 0x00010203 0x83828180 0x87868584 0x8B8A8988 0x8F8E8D8C
// least significant 32-bits
// most significant 32-bits
Let us now see how this value may be represented in the CPU main memory for different types of CPUs and various data value formats.
2
Little-endian CPU, little-endian data in memory
An example would be an Intel family CPU (e.g., Pentium) where data is kept in the 'natural' CPU order. At the byte level, the value of N in memory would be, in order of increasing memory address, starting at address X:
X X+8 X+16 X+24 : : : : 0x0F 0x07 0x80 0x88 0x0E 0x06 0x81 0x89 0x0D 0x05 0x82 0x8A 0x0C 0x04 0x83 0x8B 0x0B 0x03 0x84 0x8C 0x0A 0x02 0x85 0x8D 0x09 0x01 0x86 0x8E 0x08 0x00 0x87 0x8F
At the 32-bit word level, these bytes correspond to
X X+4 X+8 X+12 X+16 X+20 X+24 X:28 : : : : : : : : 0x0C0D0E0F 0x08090A0B 0x04050607 0x00010203 0x83828180 0x87868584 0x8B8A8988 0x8F8E8D8C
Note that, given this byte and word ordering in memory, the CPU can simply perform a memory move operation of length 32 bytes from address X to register offset 0x1E0 to register r3 in window 2. In 32-bit Intel assembly language, the data could be moved from memory into the 6500 as follows: mov mov mov add edi,ADDR_6500_BASE eax,256 [edi+100Ch],eax edi,41E0h ; base address of the 6500 ; bit length ; set the length tag for r3 ; point to register r3, window 2 ; (left justify the 256-bit value) ; incrementing addresses ; start moving dwords from X ; move 8 dwords (256 bits) ; move the value from memory to r3
cld lea esi,X mov ecx,256/32 rep movsd
In other words, the sequence of operations is:
Memory read 6500 write Internal register write ----------------------------------------------------------- 0x41E0 0x01E0 X : 0x0C0D0E0F 0x0C0D0E0F 0x41E4 0x01E4 X+4 : 0x08090A0B 0x08090A0B 0x41E8 0x01E8 X+8 : 0x04050607 0x04050607
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6500 Data Windowing Examples
X+12 X+16 X+20 X+24 X:28 : : : : : 0x00010203 0x83828180 0x87868584 0x8B8A8988 0x8F8E8D8C

0x41EC 0x41F0 0x41F4 0x41F8 0x41FC
0x00010203 0x83828180 0x87868584 0x8B8A8988 0x8F8E8D8C

0x01EC 0x01F0 0x01F4 0x01F8 0x01FC
3
Little-endian CPU, big-endian data in memory
In many network protocols (e.g, IPSEC), the network byte ordering for publickey integer quantities is big-endian. In other words, the most significant byte of integer values used for RSA or Diffie-Hellman computations is sent over the line first, with the least significant byte last. Thus, even for a little-endian CPU such as the Intel Pentium, the data is stored in memory in big-endian order. When the public-key computations are performed in software, usually the first step is to convert from big-endian to little-endian. However, the 6500 windowing scheme allows simple transfers without any reordering in memory, as we shall see below. At the byte level, the value of N in memory would be, in order of increasing memory address, starting at address Y:
Y Y+8 Y+16 Y+24 : : : : 0x8F 0x87 0x00 0x08 0x8E 0x86 0x01 0x09 0x8D 0x85 0x02 0x0A 0x8C 0x84 0x03 0x0B 0x8B 0x83 0x04 0x0C 0x8A 0x82 0x05 0x0D 0x89 0x81 0x06 0x0E 0x88 0x80 0x07 0x0F
At the 32-bit word level, these bytes appear to the CPU as
Y Y+4 Y+8 Y+12 Y+16 Y+20 Y+24 Y+28 : : : : : : : : 0x8C8D8E8F 0x88898A8B 0x84858687 0x80818283 0x03020100 0x07060504 0x0B0A0908 0x0F0E0D0C
Note that these 32-bit word values would be incorrect if the CPU tried to interpret them directly. However, given this byte and word ordering in memory, the little-endian CPU can simply perform a memory move operation of length 32 bytes from address Y to register offset 0x180 to register r3 in window 1, without any software transformations required. Because window 1 reverses the order of the word registers, the first 32-bit write to offset 0x6180 actually goes to internal data register address 0x1FC, which is the most significant word of the register. Because window 1 reverses the byte ordering, the conversion from big-endian to little-endian is also performed automatically by the 6500. In 32-bit Intel assembly language, the data could be moved from memory into the 6500 as follows: mov mov mov add cld lea edi,ADDR_6500_BASE eax,256 [edi+100Ch],eax edi,2180h esi,Y ; base address of the 6500 ; bit length ; set the length tag for r3 ; point to register r3, window 3 ; incrementing addresses ; start moving dwords from Y
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6500 Data Windowing Examples mov ecx,256/32 rep movsd ; move 8 dwords (256 bits) ; move the value from memory to r3
In other words, the sequence of operations is:
Memory read 6500 write Internal register write ----------------------------------------------------------- 0x2180 0x01FC Y : 0x8C8D8E8F 0x8F8E8D8C 0x2184 0x01F8 Y+4 : 0x88898A8B 0x8B8A8988 0x2188 0x01F4 Y+8 : 0x84858687 0x87868584 0x218C 0x01F0 Y+12 : 0x80818283 0x83828180 0x2190 0x01EC Y+16 : 0x03020100 0x00010203 0x2194 0x01E8 Y+20 : 0x07060504 0x04050607 0x2198 0x01E4 Y+24 : 0x0B0A0908 0x08090A0B 0x219C 0x01E0 Y+28 : 0x0F0E0D0C 0x0C0D0E0F
4
Big-endian CPU, big-endian data in memory
On a big-endian CPU, such as the Motorola 68000 family, the IPSEC byte ordering is very natural for software public key computations. The 6500 windowing allows very simple transfers between CPU memory and the 6500 data registers. At the byte level, the value of N in memory would be, in order of increasing memory address, starting at address Z:
Z Z+8 Z+16 Z+24 : : : : 0x8F 0x87 0x00 0x08 0x8E 0x86 0x01 0x09 0x8D 0x85 0x02 0x0A 0x8C 0x84 0x03 0x0B 0x8B 0x83 0x04 0x0C 0x8A 0x82 0x05 0x0D 0x89 0x81 0x06 0x0E 0x88 0x80 0x07 0x0F
At the 32-bit word level, these bytes appear to the CPU as
Z Z+4 Z+8 Z+12 Z+16 Z+20 Z+24 Z+28 : : : : : : : : 0x8F8E8D8C 0x8B8A8988 0x87868584 0x83828180 0x00010203 0x04050607 0x08090A0B 0x0C0D0E0F
Given this byte and word ordering in memory, the little-endian CPU can simply perform a memory move operation of length 32 bytes from address Y to register offset 0x180 to register r3 in window 3, without any software transformations required. Because window 3 reverses the order of the word registers, the first 32bit write to offset 0x6180 actually goes to internal data register address 0x1FC, which is the most significant word of the register. Note that no endian conversion is required, since it is assumed that the CPU is wired to the 6500 data bus so that the most (and least) significant data bits of the two chips are connected.
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6500 Data Windowing Examples In 68000 assembly language, the data could be moved from memory into the 6500 as follows: lea mov.L mov.L add.L mov.L lea mov.L dbra (ADDR_6500_BASE),a0 #256,d0 d0,100Ch(a0) #6180h,a0 #(256/32)-1,d1 (Z),a1 (a1)++,(a0)++ d1,movLp ; base address of the 6500 ; bit length ; set the length tag for r3 ; point to register r3, window 1 ; move 8 longwords (256 bits) ; start moving longwords from Z ; move one longword ; loop until done
movLp:
In other words, the sequence of operations is:
Memory read 6500 write Internal register write ----------------------------------------------------------- 0x6180 0x01FC 0x8F8E8D8C Z : 0x8F8E8D8C 0x6184 0x01F8 Z+4 : 0x8B8A8988 0x8B8A8988 0x6188 0x01F4 Z+8 : 0x87868584 0x87868584 0x618C 0x01F0 Z+12 : 0x83828180 0x83828180 0x6190 0x01EC Z+16 : 0x00010203 0x00010203 0x6194 0x01E8 Z+20 : 0x04050607 0x04050607 0x6198 0x01E4 Z+24 : 0x08090A0B 0x08090A0B 0x619C 0x01E0 Z+28 : 0x0C0D0E0F 0x0C0D0E0F
5
Big-endian CPU, little-endian data in memory
This scenario could occur with a big-endian CPU using a protocol with littleendian network ordering of public-key quantities. Since no such protocol of any importance is known, this case is left as an exercise for the reader. Window 1 of the 6500 would be used to re-order both bytes and words.
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